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1 file number 4521.4 hi5660 8-bit, 165/125/60msps, high speed d/a converter the hi5660 is an 8-bit, 125msps, high speed, low power, d/a converter which is implemented in an advanced cmos process. operating from a single +3v to +5v supply, the converter provides 20ma of full scale output current and includes edge-triggered cmos input data latches. low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. for an equivalent performance dual version, see the hi5628. this device complements the commlink hi5x60 family of high speed converters offered by intersil, which includes 8, 10, 12, and 14-bit devices. ? contact factory for availability. features throughput rate . . . . . . . . . . . . . . . . . . . . . . . .125msps low power . . . . . . . . . . . . . . . 165mw at 5v, 27mw at 3v power down mode . . . . . . . . . . 23mw at 5v, 10mw at 3v integral linearity error . . . . . . . . . . . . . . . . . . . 0.25 lsb adjustable full scale output current . . . . . 2ma to 20ma sfdr to nyquist at 10mhz output . . . . . . . . . . . . .60dbc internal 1.2v bandgap voltage reference single power supply from +5v to +3v cmos compatible inputs excellent spurious free dynamic range applications medical instrumentation wireless communications direct digital frequency synthesis signal reconstruction test instrumentation high resolution imaging systems arbitrary waveform generators pinout hi5660 (soic, tssop) top view ordering information part number temp. range ( o c) package pkg. no. clock speed hi5660/16ib ? -40 to 85 28 ld soic m28.3 165mhz hi5660/16ia ? -40 to 85 28 ld tssop m28.173 165mhz HI5660IB -40 to 85 28 ld soic m28.3 125mhz hi5660ia ? -40 to 85 28 ld tssop m28.173 125mhz hi5660/6ib ? -40 to 85 28 ld soic m28.3 60mhz hi5660/6ia -40 to 85 28 ld tssop m28.173 60mhz hi5660eval1 ? 25 evaluation platform 125mhz 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) dcom dcom dcom dcom dcom dcom 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clk dcom nc av dd nc ioutb comp1 fsadj refio reflo sleep dv dd iouta acom data sheet november 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999 commlink is a trademark of intersil corporation.
2 typical applications circuit functional block diagram d7 (msb) (1) d6 (2) d5 (3) d4 (4) d3 (5) d2 (6) d1 (7) d0 (lsb) (8) d7 d6 d5 d4 d3 d2 d1 d0 dcom (26) clk (28) (19) comp1 (24) av dd d/a out (22) iouta (21) ioutb 50 ? (18) fsadj (16) reflo hi5660 dv dd (27) +5v or +3v (v dd ) 0.1 f 50 ? 10 f (20) acom 50 ? (15) sleep (17) refio 0.1 f 1.91k ? ferrite 10 h 0.1 f (23) nc 0.1 f d/a out + bead r set (9-14, 25) dcom dcom acom 10 f + ferrite 10 h bead upper voltage reference (lsb) d0 d1 d2 d3 d4 (msb) d7 clk d5 d6 5-bit decoder refio latch av dd acom dv dd dcom latch cascode current source switch matrix bias generation int/ext fsadj reference int/ext select reflo 31 34 34 31 msb segments 3 lsbs + comp1 sleep iouta ioutb hi5660
3 absolute maximum ratings thermal information digital supply voltage dv dd to dcom . . . . . . . . . . . . . . . . . . +5.5v analog supply voltage av dd to acom . . . . . . . . . . . . . . . . . . +5.5v grounds, acom to dcom. . -0.3v to +0.3v digital input voltages (d9-d0, clk, sleep) . . . . . . . . . . . . . . . . . . . . . . . . . dv dd + 0.3v internal reference output current. . . . . . . . . . . . . . . . . . . . . 50 a reference input voltage range . . . . . . . . . . . . . . . . . . av dd + 0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 tssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations av dd = dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values parameter test conditions t a = -40 o c to 85 o c units min typ max system performance resolution 8 - - bits integral linearity error, inl ?est fit?straight line (note 7) -0.5 0.25 +0.5 lsb differential linearity error, dnl (note 7) -0.5 0.25 +0.5 lsb offset error, i os (note 7) -0.025 +0.025 % fsr offset drift coefficient (note 7) - 0.1 - ppm fsr/ o c full scale gain error, fse with external reference (notes 2, 7) -10 2 +10 % fsr with internal reference (notes 2, 7) -10 1 +10 % fsr full scale gain drift with external reference (note 7) - 50 - ppm fsr/ o c with internal reference (note 7) - 100 - ppm fsr/ o c full scale output current, i fs 2 - 20 ma output voltage compliance range (note 3) -0.3 - 1.25 v dynamic characteristics maximum clock rate, f clk (notes 3, 9) 125 - - mhz output settling time, (t sett ) 0.8% ( 1 lsb, equivalent to 7 bits) (note 7) - 5 - ns 0.4% ( 1/2 lsb, equivalent to 8 bits) (note 7) - 15 - ns singlet glitch area (peak glitch) r l = 25 ? (note 7) - 5 - pv? output rise time full scale step - 1.5 - ns output fall time full scale step - 1.5 - ns output capacitance 10 pf output noise ioutfs = 20ma - 50 - pa/ hz ioutfs = 2ma - 30 - pa/ hz ac characteristics hi5660/16ib, hi5660/16ia - 165mhz spurious free dynamic range, sfdr within a window f clk = 165msps, f out = 66.7mhz, 50mhz span (notes 4, 7, 9) - 60 - dbc f clk = 165msps, f out = 20.2mhz, 30mhz span (notes 4, 7, 9) - 69 - dbc f clk = 125msps, f out = 32.9mhz, 10mhz span (notes 4, 7) - 70 - dbc f clk = 100msps, f out = 5.04mhz, 4mhz span (notes 4, 7) - 73 - dbc hi5660
4 total harmonic distortion (thd) to nyquist f clk = 165msps, f out = 8.2mhz (notes 4, 7) - 64 - dbc f clk = 100msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc spurious free dynamic range, sfdr to nyquist f clk = 165msps, f out = 66.7mhz, 82.5mhz span (notes 4, 7, 9) - 46 - dbc f clk = 165msps, f out = 20.2mhz, 82.5mhz span (notes 4, 7, 9) - 54 - dbc f clk = 125msps, f out = 32.9mhz, 62.5mhz span (notes 4, 7) - 51 - dbc f clk = 125msps, f out = 10.1mhz, 62.5mhz span (notes 4, 7) - 61 - dbc f clk = 100msps, f out = 40.4mhz, 50mhz span (notes 4, 7) - 48 - dbc f clk = 100msps, f out = 20.2mhz, 50mhz span (notes 4, 7) - 56 - dbc f clk = 100msps, f out = 5.04mhz, 50mhz span (notes 4, 7) - 68 - dbc ac characteristics HI5660IB, hi5660ia - 125mhz spurious free dynamic range, sfdr within a window f clk = 125msps, f out = 32.9mhz, 10mhz span (notes 4, 7) - 70 - dbc f clk = 100msps, f out = 5.04mhz, 4mhz span (notes 4, 7) - 73 - dbc total harmonic distortion (thd) to nyquist f clk = 100msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc spurious free dynamic range, sfdr to nyquist f clk = 125msps, f out = 32.9mhz, 62.5mhz span (notes 4, 7) - 51 - dbc f clk = 125msps, f out = 10.1mhz, 62.5mhz span (notes 4, 7) - 61 - dbc f clk = 100msps, f out = 40.4mhz, 50mhz span (notes 4, 7) - 48 - dbc f clk = 100msps, f out = 20.2mhz, 50mhz span (notes 4, 7) - 56 - dbc f clk = 100msps, f out = 5.04mhz, 50mhz span (notes 4, 7) - 68 - dbc f clk = 100msps, f out = 2.51mhz, 50mhz span (notes 4, 7) - 68 - dbc ac characteristics hi5660/6ib, hi5660/6ia - 60mhz spurious free dynamic range, sfdr within a window f clk = 60msps, f out = 10.1mhz, 10mhz span (notes 4, 7) - 62 - dbc f clk = 50msps, f out = 5.02mhz, 2mhz span (notes 4, 7) - 73 - dbc f clk = 50msps, f out = 1.00mhz, 2mhz span (notes 4, 7) - 74 - dbc total harmonic distortion (thd) to nyquist f clk = 50msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc f clk = 50msps, f out = 1.00mhz (notes 4, 7) - 68 - dbc spurious free dynamic range, sfdr to nyquist f clk = 60msps, f out = 20.2mhz, 30mhz span (notes 4, 7) - 54 - dbc f clk = 60msps, f out = 10.1mhz, 30mhz span (notes 4, 7) - 60 - dbc f clk = 50msps, f out = 20.2mhz, 25mhz span (notes 4, 7) - 53 - dbc f clk = 50msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 67 - dbc f clk = 50msps, f out = 2.51mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 50msps, f out = 1.00mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 25msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 71 - dbc voltage reference internal reference voltage, v fsadj voltage at pin 18 with internal reference 1.04 1.16 1.28 v internal reference voltage drift - 60 - ppm / o c internal reference output current sink/source capability - 0.1 - a reference input impedance -1 -m ? reference input multiplying bandwidth (note 7) - 1.4 - mhz digital inputs d7-d0, clk input logic high voltage with 5v supply, v ih (note 3) 3.5 5 - v input logic high voltage with 3v supply, v ih (note 3) 2.1 3 - v electrical speci?ations av dd = dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values (continued) parameter test conditions t a = -40 o c to 85 o c units min typ max hi5660
5 input logic low voltage with 5v supply, v il (note 3) - 0 1.3 v input logic low voltage with 3v supply, v il (note 3) - 0 0.9 v input logic current, i ih -10 - +10 a input logic current, i il -10 - +10 a digital input capacitance, c in -5 - pf timing characteristics data setup time, t su see figure 3 (note 3) 3 - - ns data hold time, t hld see figure 3 (note 3) 3 - - ns propagation delay time, t pd see figure 3 - 1 - ns clk pulse width, t pw1 , t pw2 see figure 3 (note 3) 4 - - ns power supply characteristics av dd power supply (note 8, 9) 2.7 5.0 5.5 v dv dd power supply (note 8, 9) 2.7 5.0 5.5 v analog supply current (i avdd ) 5v or 3v, ioutfs = 20ma - 23 30 ma 5v or 3v, ioutfs = 2ma - 4 - ma digital supply current (i dvdd ) 5v, ioutfs = don? care (note 5) - 3 5 ma 3v, ioutfs = don? care (note 5) - 1.5 - ma supply current (i avdd ) sleep mode 5v or 3v, ioutfs = don? care - 1.6 3 ma power dissipation 5v, ioutfs = 20ma (note 6) - 165 - mw 5v, ioutfs = 20ma (note 10) - 150 - mw 5v, ioutfs = 2ma (note 6) - 70 - mw 3.3v, ioutfs = 20ma (note 10) - 75 - mw 3v, ioutfs = 20ma (note 6) - 85 - mw 3v, ioutfs = 20ma (note 10) - 67 - mw 3v, ioutfs = 2ma (note 6) - 27 - mw power supply rejection single supply (note 7) -0.2 - +0.2 % fsr/v notes: 2. gain error measured as the error in the ratio between the full scale output current and the current through r set (typically 625 a). ideally the ratio should be 32. 3. parameter guaranteed by design or characterization and not production tested. 4. spectral measurements made with differential transformer coupled output and no external filtering. 5. measured with the clock at 50msps and the output frequency at 1mhz. 6. measured with the clock at 100msps and the output frequency at 40mhz. 7. see ?efinition of specifications? 8. it is recommended that the output current be reduced to 12ma or less to maintain optimum performance for operation below 3v. dv dd and av dd do not have to be equal. 9. for operation above 125mhz, it is recommended that the power supply be 3.3v or greater. the part is functional with the clock above 125msps and the power supply below 3.3v, but performance is degraded (valid for 165mhz version only). 10. measured with the clock at 60msps and the output frequency at 10mhz. electrical speci?ations av dd = dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values (continued) parameter test conditions t a = -40 o c to 85 o c units min typ max hi5660
6 timing diagrams figure 1. output settling time diagram figure 2. peak glitch area (singlet) measurement method figure 3. propagation delay, setup time, hold time and minimum pulse width diagram clk d7-d0 i out 50% t sett 1 / 2 lsb error band t pd v t(ps) height (h) width (w) glitch area = 1 / 2 (h x w) clk i out 50% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld t sett t sett t sett d7-d0 hi5660
7 de?ition of speci?ations integral linearity error, inl, is the measure of the worst case point that deviates from a best ? straight line of data values along the transfer curve. differential linearity error, dnl, is the measure of the step size output deviation from code to code. ideally the step size should be 1 lsb. a dnl speci?ation of 1 lsb or less guarantees monotonicity. output settling time, is the time required for the output voltage to settle to within a speci?d error band measured from the beginning of the output transition. in the case of the hi5660, the measurement was done by switching from code 0 to 64, or quarter scale. termination impedance was 25 ? due to the parallel resistance of the output 50 ? and the oscilloscopes 50 ? input. this also aids the ability to resolve the speci?d error band without overdriving the oscilloscope. singlet glitch area, is the switching transient appearing on the output during a code transition. it is measured as the area under the overshoot portion of the curve and is expressed as a volt-time speci?ation. full scale gain error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through r set ). full scale gain drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from t min to t max . it is de?ed as the maximum deviation from the value measured at room temperature to the value measured at either t min or max . the units are ppm of fsr (full scale range) per degree c. total harmonic distortion, thd , is the ratio of the dac output fundamental to the rms sum of the first five harmonics. spurious free dynamic range, sfdr, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the speci?d window. output voltage compliance range, is the voltage limit imposed on the output. the output impedance load should be chosen such that the voltage developed does not violate the compliance range. offset error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. offset error is de?ed as the maximum deviation of the output current from a value of 0ma. offset drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from t min to max .it is de?ed as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per degree c. power supply rejection, is measured using a single power supply. its nominal +5v is varied 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is de?ed as the 3db bandwidth of the voltage reference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the frequency is increased until the amplitude of the output waveform is 0.707 of its original value. internal reference voltage drift, is de?ed as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm per degree c. detailed description the hi5660 is an 8-bit, current out, cmos, digital to analog converter. its maximum update rate is 165msps and can be powered by either single or dual power supplies in the recommended range of +3v to +5v. it consumes less than 165mw of power when using a +5v supply with the data switching at 100msps. the architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. the ?e msbs are represented by 31 major current sources of equivalent current. the three lsbs are comprised of binary weighted current sources. consider an input pattern to the converter which ramps through all the codes from 0 to 255. the three lsb current sources would begin to count up. when they reached the all high state (decimal value of 7) and needed to count to the next code, they would all turn off and the ?st major current source would turn on. to continue counting upward, the 3 lsbs would count up another 7 codes, and then the next major current source would turn on and the three lsbs would all turn off. the process of the single, equivalent, major current source turning on and the three lsbs turning off each time the converter reaches another 7 codes greatly reduces the glitch at any one switching point. in previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst- case transition points such as midscale and quarter scale transitions. by greatly reducing the amount of current switching at certain ?ajor?transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems. digital inputs and termination the hi5660 digital inputs are guaranteed to cmos levels. however, ttl compatibility can be achieved by lowering the supply voltage to 3v due to the digital threshold of the input buffer being approximately half of the supply voltage. the internal register is updated on the rising edge of the clock. to minimize re?ctions, proper termination should be implemented. if the lines driving the clock and the digital hi5660
8 inputs are 50 ? lines, then 50 ? termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). ground plane(s) if separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. the same is true for the analog components and the analog ground plane. noise reduction to minimize power supply noise, 0.1 f capacitors should be placed as close as possible to the converters power supply pins, av dd and dv dd . also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on the board is recommended. voltage reference the internal voltage reference of the device has a nominal value of +1.2v with a 60 ppm/ o c drift coefficient over the full temperature range of the converter. it is recommended that a 0.1 f capacitor be placed as close as possible to the refio pin, connected to the analog ground. the reflo pin (16) selects the reference. the internal reference can be selected if pin 16 is tied low (ground). if an external reference is desired, then pin 16 should be tied high (to the analog supply voltage) and the external reference driven into refio, pin 17. the full scale output current of the converter is a function of the voltage reference used and the value of r set .i out should be within the 2ma to 20ma range, through operation below 2ma is possible, with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.16v (pin 18). if an external reference is used, v fsadj will equal the external reference. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set )x 32. if the full scale output current is set to 20ma by using the internal voltage reference (1.16v) and a 1.86k ? r set resistor, then the input coding to output current will resemble the following: outputs iouta and ioutb are complementary current outputs. the sum of the two currents is always equal to the full scale output current minus one lsb. if single ended use is desired, a load resistor can be used to convert the output current to a voltage. it is recommended that the unused output be either grounded or equally terminated. the voltage developed at the output must not violate the output voltage compliance range of -0.3v to 1.25v. r load should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the ?eference?section. if a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. the output voltage equation is: v out = i out x r load . these outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. the sfdr measurements in this data sheet were performed with a 1:1 transformer on the output of the dac (see figure 1). with the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. it is important to note here that the negative voltage output compliance range limit is -300mv, imposing a maximum of 600mv p-p amplitude with this con?uration. the loading as shown in figure 1 will result in a 500mv signal at the output of the transformer if the full scale output current of the dac is set to 20ma. v out = 2 x i out x r eq , where r eq is ~12.5 ? . table 1. input coding vs output current input code (d7-d0) iouta (ma) ioutb (ma) 111 11111 20 0 100 00000 10 10 000 00000 0 20 pin 21 pin 22 v out = (2 x i out x r eq )v 100 ? hi5660 50 ? 50 ? 50 ? ioutb iouta figure 4. hi5660
9 pin descriptions pin no. pin name pin description 1-8 d7 (msb) through d0 (lsb) digital data bit 7, (most significant bit) through digital data bit 0, (least significant bit). 9-14 dcom connect to digital ground. 15 sleep control pin for power-down mode. sleep mode is active high; connect to ground for normal mode. sleep pin has internal 20 a active pulldown current. 16 reflo connect to analog ground to enable internal 1.2v reference or connect to av dd to disable internal refer- ence. 17 refio ref erence voltage input if internal reference is disabled. reference voltage output if internal reference is en- abled. use 0.1 f cap to ground when internal reference is enabled. 18 fsadj full scale current adjust. use a resistor to ground to adjust full scale output current. full scale output current = 32 x v fsadj /r set . 19 comp1 for use in reducing bandwidth/noise. recommended: connect 0.1 f to av dd . 20 acom analog ground. 21 ioutb the complimentary current output of the device. full scale output current is achieved when all input bits are set to binary 0. 22 iouta current output of the device. full scale output current is achieved when all input bits are set to binary 1. 23 nc internally connected to acom via a resistor. recommend leave disconnected. adding a capacitor to acom for upward compatibility is valid. grounding to acom is valid. (for upward compatibility to 12-bit and 14-bit devices, pin 23 needs the ability to have a 0.1 f capacitor to acom.) 24 av dd analog supply (+3v to +5v). 25 nc no connect (for upward compatibility to 12 and 14b, pin 25 needs to be grounded to acom). 26 dcom digital ground. 27 dv dd digital supply (+3v to +5v). 28 clk input for clock. positive edge of clock latches data. hi5660
10 hi5660 thin shrink small outline plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are within allowable dimensions of jedec mo-153-ae, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?1 does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ? dimen- sion at maximum material condition. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m28.173 28 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.378 0.386 9.60 9.80 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 6/98
11 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hi5660 small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93

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